The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to an improved boost reset circuit for a flash memory.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing supply voltage levels. Previous circuit families operated at 5 volts and 3.3 volts. Current families operate at 1.8 volts and future families will operate at 1.0 volts nominal supply voltage. These lower supply voltages create design and operation problems.
One design problem relates to accessing a core cell of the memory device. The voltage swing available in a 1.0 volt supply system is typically insufficient for a read or a program of a flash memory cell. Accordingly, boost circuits have been developed to provide the necessary voltage variation. For accessing the core cell, a word line voltage is boosted to, for example, 4.0 volts. This allows the core cell transistor to fully turn on and the core cell to sink enough current for rapid sensing of the state of the cell.
To control operation of the boost circuit, particularly when many address inputs are changing, a reset circuit is incorporated in the boost circuit. The reset circuit responds to address transitions by resetting the boosted voltage to a reset value. However, the reduction in supply voltage for the memory to 1.0 volts. interferes with the operation of the reset circuit. A p-channel transistor used for resetting the boosted voltage cannot be adequately turned on at low supply voltage to ensure rapid reset.
Accordingly, an improved reset circuit for a boost circuit for a memory device is required for operation at reduced supply voltages.